The present invention generally relates to high-temperature superconductor (HTS) junctions, and in particular to self-aligned thin barrier HTS edge junctions.
With increasing demand on processing efficiency and speed of computing for computer and communication systems, HTS circuits have been utilized to perform high speed analog-to-digital (ADC) and digital-to-analog (DAC) operations such as 5 Gsps 8 bit, and logic functions such as 5 Gbps, at low power consumption for a wide range of applications in military and commercial systems.
In particular, HTS superconductor-normal conductor-superconductor (SNS) edge junctions have been utilized to provide high speed, low power operations in HTS integrated circuits to perform various ADC, DAC and digital functions. However, a major disadvantage of existing SNS junctions is excessive parasitic inductance, which requires the use of junctions with low critical current (Ic), and critical current to normal resistance (IcRn) product. A low IcRn product results in lower speed of operation of HTS circuits integrating existing SNS junctions.
There is, therefore, a need for an SNS junction which reduces parasitic inductance while preserving the IcRn product needed to realize low power, high speed advantages of HTS circuits.